report_05-07-2025_03-17-10.html

Report generated on 07-May-2025 at 03:23:04 by pytest-html v3.2.0

Summary

2000 tests ran in 353.88 seconds.

1993 passed, 0 skipped, 7 failed, 0 errors, 0 expected failures, 0 unexpected passes

Results

Result Test TIDL Subgraphs Complete TIDL Offload Duration Links
Failed test_tidl_unit.py::test_tidl_unit_operator[Resize_1600] 1 True 31.00
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Resize_1600'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Resize_1600', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Resize'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-25' pid=2762551 parent=2721529 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== [TIDL Import] WARNING: Resize layer - with 'align_corners' coordinate_transformation_mode is not optimal The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2712s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2725s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ [TIDL Import] FATAL ERROR: Network Compiler failed to execute - Memory planning failed with return code - 35584 -- [tidl_import_core.cpp, 1051] [TIDL Import] Aborting
------------------------------Captured stderr call------------------------------
Segmentation fault (core dumped)
Failed test_tidl_unit.py::test_tidl_unit_operator[Resize_783] 1 True 44.64
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Resize_783'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Resize_783', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Resize'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=2771222 parent=2721372 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.477s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7081s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7095s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ [TIDL Import] FATAL ERROR: Network Compiler failed to execute - Memory planning failed with return code - 35584 -- [tidl_import_core.cpp, 1051] [TIDL Import] Aborting
------------------------------Captured stderr call------------------------------
Segmentation fault (core dumped)
Failed test_tidl_unit.py::test_tidl_unit_operator[Resize_896] 1 True 39.99
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Resize_896'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Resize_896', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Resize'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-39' pid=2772731 parent=2721594 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== [TIDL Import] WARNING: Resize layer - with 'align_corners' coordinate_transformation_mode is not optimal The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.262s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4040s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4054s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ [TIDL Import] FATAL ERROR: Network Compiler failed to execute - Memory planning failed with return code - 35584 -- [tidl_import_core.cpp, 1051] [TIDL Import] Aborting
------------------------------Captured stderr call------------------------------
Segmentation fault (core dumped)
Failed test_tidl_unit.py::test_tidl_unit_operator[Resize_1196] 1 True 33.19
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Resize_1196'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Resize_1196', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Resize'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-39' pid=2780051 parent=2721800 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.36s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.498s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8653s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8680s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ [TIDL Import] FATAL ERROR: Network Compiler failed to execute - Memory planning failed with return code - 35584 -- [tidl_import_core.cpp, 1051] [TIDL Import] Aborting
------------------------------Captured stderr call------------------------------
Segmentation fault (core dumped)
Failed test_tidl_unit.py::test_tidl_unit_operator[Resize_653] 1 True 37.40
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Resize_653'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Resize_653', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Resize'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-51' pid=2811807 parent=2721389 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.526s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9074s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9101s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ [TIDL Import] FATAL ERROR: Network Compiler failed to execute - Memory planning failed with return code - 35584 -- [tidl_import_core.cpp, 1051] [TIDL Import] Aborting
------------------------------Captured stderr call------------------------------
Segmentation fault (core dumped)
Failed test_tidl_unit.py::test_tidl_unit_operator[Resize_731] 1 True 16.55
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Resize_731'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Resize_731', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Resize'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-83' pid=2845841 parent=2722128 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal [TIDL Import] WARNING: Resize layer - output with 'round_prefer_floor' nearest mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== [TIDL Import] WARNING: Resize layer - with 'round_prefer_floor' nearest mode is not optimal The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.158s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1613s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1617s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ [TIDL Import] FATAL ERROR: Network Compiler failed to execute - Memory planning failed with return code - 35584 -- [tidl_import_core.cpp, 1051] [TIDL Import] Aborting
------------------------------Captured stderr call------------------------------
Segmentation fault (core dumped)
Failed test_tidl_unit.py::test_tidl_unit_operator[Resize_1676] 1 True 15.27
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Resize_1676'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Resize_1676', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Resize'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-104' pid=2847259 parent=2721659 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.131s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1311s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1324s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ [TIDL Import] FATAL ERROR: Network Compiler failed to execute - Memory planning failed with return code - 35584 -- [tidl_import_core.cpp, 1051] [TIDL Import] Aborting
------------------------------Captured stderr call------------------------------
Segmentation fault (core dumped)
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_899] 0 - 4.79
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1832] 0 - 0.62
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_915] 0 - 0.40
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1229] 0 - 0.59
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_122] 1 True 17.12
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.260s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2332s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2343s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 89769857 bytes MEM: Free's : 26 free's of 89769857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1453] 0 - 0.14
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1148] 1 True 10.57
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2751s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2758s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_873] 0 - 0.25
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_841] 1 True 23.29
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.575s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8204s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8227s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 247024861 bytes MEM: Free's : 26 free's of 247024861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1286] 0 - 0.36
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_654] 1 True 15.43
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.375s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4540s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4562s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1608] 0 - 0.68
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1817] 0 - 0.18
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1195] 0 - 0.21
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1675] 0 - 0.34
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1976] 0 - 4.17
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1862] 0 - 0.17
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1783] 0 - 0.38
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1544] 0 - 0.31
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1548] 0 - 0.85
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_921] 0 - 0.32
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_395] 0 - 0.14
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_836] 0 - 0.15
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1558] 1 True 16.55
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.382s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7106s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7124s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_198] 0 - 0.32
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_112] 0 - 0.57
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_981] 0 - 0.39
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_307] 0 - 0.35
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1052] 0 - 0.48
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_617] 0 - 0.40
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1488] 0 - 1.16
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1307] 0 - 0.63
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_386] 0 - 0.45
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_878] 0 - 0.95
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_628] 0 - 0.36
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1635] 0 - 0.42
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_564] 1 True 17.69
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.399s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5026s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5041s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_983] 0 - 0.37
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_8] 0 - 0.33
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1037] 0 - 0.39
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1021] 0 - 0.70
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_166] 1 True 14.41
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9076s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9098s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_798] 1 True 15.26
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.324s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3424s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3439s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1292] 0 - 0.47
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1445] 0 - 0.39
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1935] 0 - 0.39
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1025] 0 - 0.39
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_146] 1 True 12.70
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.250s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3556s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3565s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1879] 0 - 0.38
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_532] 0 - 0.35
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_485] 1 True 10.81
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4577s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4591s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_840] 1 True 15.66
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== [TIDL Import] WARNING: Resize layer - with 'align_corners' coordinate_transformation_mode is not optimal The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.536s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7035s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7057s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= [TIDL Import] WARNING: Resize layer - with 'align_corners' coordinate_transformation_mode is not optimal ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 103007693 bytes MEM: Free's : 26 free's of 103007693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1191] 0 - 0.46
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1826] 0 - 0.32
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1048] 0 - 0.38
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1355] 0 - 0.29
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_114] 0 - 0.34
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_325] 0 - 0.46
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1484] 0 - 0.39
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_926] 0 - 0.43
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1984] 0 - 0.33
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_608] 1 True 18.60
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.281s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4206s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4224s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 788633021 bytes MEM: Free's : 26 free's of 788633021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_63] 1 True 16.61
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.376s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4897s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4909s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_817] 0 - 0.26
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_169] 0 - 0.43
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_280] 0 - 0.37
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_487] 0 - 3.53
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_782] 0 - 1.47
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1874] 0 - 0.57
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_93] 0 - 0.66
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1876] 0 - 5.57
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_936] 1 True 17.41
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.422s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6383s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6402s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 89769857 bytes MEM: Free's : 26 free's of 89769857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1670] 0 - 0.48
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_681] 0 - 0.42
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_912] 0 - 0.47
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1669] 0 - 0.41
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1466] 0 - 1.39
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_937] 0 - 0.95
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1489] 1 True 10.61
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3585s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3597s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_600] 0 - 0.60
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1483] 1 True 12.60
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.442s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7697s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7716s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_672] 0 - 0.55
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1772] 0 - 0.43
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_927] 1 True 12.27
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.459s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5118s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5133s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_420] 0 - 0.36
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1942] 0 - 0.74
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1088] 0 - 0.58
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1271] 0 - 0.42
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_949] 0 - 0.37
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1175] 0 - 0.77
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1321] 0 - 0.31
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_463] 0 - 0.40
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_243] 0 - 1.92
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1459] 1 True 12.37
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.372s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6619s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6639s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1781] 1 True 14.46
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.209s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2201s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2212s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1116] 0 - 0.50
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_705] 0 - 0.41
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1603] 1 True 17.01
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.374s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5378s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5394s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1177] 1 True 17.12
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.471s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6124s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6138s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1899] 0 - 0.45
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_478] 1 True 16.54
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.452s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5610s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5619s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1126] 0 - 0.46
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_242] 0 - 0.40
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1146] 0 - 0.44
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1481] 0 - 0.45
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_468] 0 - 0.48
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_97] 0 - 0.46
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1855] 1 True 15.88
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.432s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8301s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8326s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1637] 0 - 0.48
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1419] 1 True 17.04
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.35s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.480s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7442s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7455s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 157895181 bytes MEM: Free's : 26 free's of 157895181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1354] 1 True 14.55
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== [TIDL Import] WARNING: Resize layer - with 'align_corners' coordinate_transformation_mode is not optimal The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.347s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10900s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10924s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= [TIDL Import] WARNING: Resize layer - with 'align_corners' coordinate_transformation_mode is not optimal ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 37705613 bytes MEM: Free's : 26 free's of 37705613 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1932] 0 - 0.46
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_407] 0 - 0.42
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1580] 1 True 15.48
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.426s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7998s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8018s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1028] 0 - 0.41
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_220] 0 - 0.31
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1625] 0 - 0.28
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_34] 1 True 10.63
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.431s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6218s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6233s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1254] 0 - 2.69
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_366] 0 - 0.26
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1687] 1 True 12.30
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.417s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6924s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6947s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1477] 0 - 0.44
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_3] 0 - 0.30
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_944] 0 - 0.47
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_183] 0 - 0.31
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_78] 1 True 19.09
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.409s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8252s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8267s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_194] 0 - 0.40
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1825] 0 - 0.41
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_538] 0 - 0.40
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_71] 0 - 0.40
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1295] 1 True 13.68
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.579s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9643s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9667s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_984] 0 - 0.35
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_435] 0 - 0.33
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_997] 0 - 0.28
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_304] 1 True 18.49
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.428s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7142s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7166s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 69729469 bytes MEM: Free's : 26 free's of 69729469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1248] 1 True 11.83
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.284s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3023s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3035s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1243] 0 - 0.38
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1824] 0 - 0.37
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_117] 0 - 0.35
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1096] 1 True 12.47
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.513s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11296s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11323s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1204] 1 True 18.53
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3604s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3614s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1462] 1 True 12.81
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.265s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2938s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2952s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21100333 bytes MEM: Free's : 26 free's of 21100333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1019] 1 True 15.34
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7993s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8011s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_604] 0 - 0.38
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_79] 0 - 0.41
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1361] 0 - 0.35
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_76] 0 - 0.47
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1594] 1 True 13.48
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.396s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8081s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8105s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1871] 0 - 0.42
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_489] 0 - 0.36
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_852] 0 - 3.40
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_614] 0 - 0.39
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_379] 0 - 0.44
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1550] 0 - 0.61
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_191] 1 True 14.92
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.34s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.37s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.582s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6784s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6810s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 81271645 bytes MEM: Free's : 26 free's of 81271645 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1793] 0 - 0.43
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1683] 0 - 0.39
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1805] 0 - 0.52
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_350] 0 - 0.46
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_774] 0 - 0.43
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_796] 1 True 13.59
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.432s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6676s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6696s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1518] 0 - 0.43
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_625] 0 - 0.61
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_23] 0 - 1.41
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1234] 1 True 13.77
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.381s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5545s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5567s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_424] 0 - 0.39
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_94] 0 - 1.42
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1799] 0 - 0.36
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1451] 0 - 0.73
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_850] 0 - 0.36
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_641] 1 True 17.49
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.334s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4963s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4985s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_577] 0 - 0.46
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_530] 0 - 0.40
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_11] 0 - 0.39
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1471] 0 - 0.47
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1156] 0 - 1.00
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_311] 0 - 0.32
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_758] 1 True 17.58
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5733s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5746s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1870] 0 - 0.55
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1236] 0 - 0.41
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_520] 0 - 0.57
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_163] 0 - 0.47
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1741] 1 True 14.48
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.241s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2347s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2357s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 103007693 bytes MEM: Free's : 26 free's of 103007693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_247] 0 - 0.53
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1155] 1 True 11.59
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.276s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2290s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2298s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1327] 0 - 0.44
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1050] 1 True 16.54
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.282s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3005s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3016s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1205] 0 - 0.43
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_289] 0 - 0.58
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1233] 0 - 0.63
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_267] 1 True 15.42
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.498s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7156s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7177s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1359] 0 - 0.41
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_639] 0 - 0.39
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_972] 0 - 0.67
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_875] 1 True 14.12
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.338s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4041s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4055s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 159042613 bytes MEM: Free's : 26 free's of 159042613 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_544] 0 - 6.24
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1443] 0 - 0.38
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1716] 1 True 11.88
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.386s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6462s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6476s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_490] 1 True 23.52
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1411s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7782s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7804s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 788633021 bytes MEM: Free's : 26 free's of 788633021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1853] 0 - 0.38
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1071] 0 - 0.39
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1818] 0 - 0.43
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_907] 0 - 0.45
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1267] 1 True 14.18
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.271s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3853s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3865s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1987] 1 True 17.56
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'round_prefer_floor' nearest mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== [TIDL Import] WARNING: Resize layer - with 'round_prefer_floor' nearest mode is not optimal The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.389s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12236s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12254s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= [TIDL Import] WARNING: Resize layer - with 'round_prefer_floor' nearest mode is not optimal ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 157895181 bytes MEM: Free's : 26 free's of 157895181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1209] 0 - 0.56
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_288] 0 - 0.35
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1523] 0 - 0.31
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1590] 0 - 0.29
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1991] 0 - 1.95
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_884] 0 - 0.35
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1939] 0 - 0.36
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_963] 0 - 0.48
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_590] 0 - 2.20
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1418] 0 - 0.74
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_991] 0 - 0.49
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_434] 0 - 0.42
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_88] 1 True 13.27
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.224s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3077s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3085s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18823909 bytes MEM: Free's : 26 free's of 18823909 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_40] 0 - 0.39
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1736] 0 - 0.33
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1708] 0 - 0.29
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1698] 0 - 0.38
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1049] 1 True 10.92
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.440s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6547s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6565s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_556] 1 True 14.64
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.232s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2895s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2909s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_43] 0 - 0.38
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1228] 1 True 12.92
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.282s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3563s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3572s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_565] 0 - 0.40
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_499] 0 - 0.34
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1222] 0 - 0.34
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1495] 0 - 16.49
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_181] 0 - 0.39
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_781] 1 True 13.99
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.367s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4098s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4110s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1778] 0 - 0.48
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1946] 0 - 0.28
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1018] 0 - 1.07
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_477] 0 - 0.39
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_95] 0 - 0.36
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_469] 0 - 0.38
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_528] 0 - 0.25
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1304] 1 True 13.74
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4319s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4332s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 40918877 bytes MEM: Free's : 26 free's of 40918877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_831] 0 - 0.47
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1100] 0 - 0.56
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_684] 0 - 0.58
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_410] 0 - 0.48
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_517] 0 - 0.49
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1399] 0 - 0.26
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_743] 1 True 15.01
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3613s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3626s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1791] 0 - 0.39
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_837] 0 - 0.50
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_202] 1 True 15.19
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.466s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6847s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6862s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_87] 0 - 0.47
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1092] 0 - 0.64
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1374] 0 - 0.40
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_59] 0 - 0.42
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_324] 0 - 0.44
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1602] 0 - 1.05
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1109] 0 - 0.52
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_713] 1 True 16.95
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.297s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3670s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3684s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_345] 1 True 17.17
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.7460s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.10731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.10859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.10922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.10977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.11075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.11140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.11209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.11274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.11366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.11438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.11492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.11540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.11661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.11727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.11791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.11847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.11893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.11944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.11996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14594s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14619s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_580] 1 True 15.66
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.419s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6113s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6137s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 99901277 bytes MEM: Free's : 26 free's of 99901277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_446] 1 True 11.96
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.431s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8184s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8205s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1812] 0 - 0.65
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_447] 0 - 0.45
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_950] 1 True 11.34
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.377s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6017s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6030s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19217125 bytes MEM: Free's : 26 free's of 19217125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_17] 0 - 0.79
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1047] 1 True 16.87
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.398s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6425s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6446s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_516] 1 True 15.51
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.520s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7301s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7317s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1246] 1 True 15.48
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'round_prefer_floor' nearest mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== [TIDL Import] WARNING: Resize layer - with 'round_prefer_floor' nearest mode is not optimal The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.98s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.99s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.517s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8191s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8214s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= [TIDL Import] WARNING: Resize layer - with 'round_prefer_floor' nearest mode is not optimal ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 159042613 bytes MEM: Free's : 26 free's of 159042613 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_982] 0 - 0.31
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_260] 0 - 0.43
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1604] 0 - 0.66
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1611] 0 - 0.47
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1516] 0 - 2.64
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1655] 0 - 0.92
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_863] 1 True 13.33
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.360s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3890s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3904s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 89769857 bytes MEM: Free's : 26 free's of 89769857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_458] 0 - 0.34
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1183] 0 - 0.32
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1740] 1 True 18.37
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.475s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7925s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7948s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1059] 0 - 0.30
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1881] 0 - 0.31
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_571] 0 - 0.53
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_599] 1 True 12.72
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.428s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11037s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11062s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_312] 1 True 13.81
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.46s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.47s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.486s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7966s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7980s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1787] 0 - 0.34
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_39] 1 True 18.16
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.278s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3515s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3524s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1494] 0 - 0.71
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_690] 0 - 0.40
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1356] 0 - 0.48
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_72] 0 - 0.49
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_403] 0 - 0.45
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1273] 0 - 0.35
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1854] 1 True 19.68
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.331s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3769s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3784s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 531413365 bytes MEM: Free's : 26 free's of 531413365 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1235] 0 - 0.94
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_110] 0 - 0.95
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1004] 0 - 0.39
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_241] 1 True 14.80
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.441s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6837s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6855s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_254] 0 - 0.36
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1615] 1 True 25.04
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal [TIDL Import] WARNING: Resize layer - output with 'round_prefer_floor' nearest mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== [TIDL Import] WARNING: Resize layer - with 'round_prefer_floor' nearest mode is not optimal The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.437s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6818s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6837s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= [TIDL Import] WARNING: Resize layer - with 'round_prefer_floor' nearest mode is not optimal ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 788633021 bytes MEM: Free's : 26 free's of 788633021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1839] 0 - 0.41
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1250] 0 - 0.39
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_380] 0 - 0.52
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_822] 1 True 13.43
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.499s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9284s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9313s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1299] 0 - 0.40
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1072] 1 True 13.13
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.281s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3043s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3060s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_579] 0 - 0.37
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_980] 1 True 18.86
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.381s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6149s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6170s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_723] 0 - 0.43
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1332] 0 - 0.37
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_911] 1 True 25.70
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.56s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.60s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.497s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7582s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7600s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 788633021 bytes MEM: Free's : 26 free's of 788633021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1130] 1 True 16.26
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.474s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8083s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8100s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_139] 0 - 0.52
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_679] 1 True 16.73
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.441s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6540s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6558s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_686] 1 True 14.24
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.286s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2726s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2739s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_177] 0 - 0.36
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_52] 0 - 0.69
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_552] 0 - 0.27
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1837] 0 - 0.36
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1952] 0 - 0.39
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_373] 0 - 0.66
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_819] 1 True 12.52
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.475s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7187s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7206s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1085] 0 - 0.35
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_578] 0 - 0.61
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1727] 0 - 0.36
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1370] 0 - 0.53
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1337] 0 - 0.44
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_634] 0 - 0.60
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_82] 0 - 0.55
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_727] 0 - 0.92
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1213] 0 - 0.31
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_776] 0 - 1.16
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_792] 0 - 0.42
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1044] 0 - 0.53
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1579] 1 True 14.03
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.411s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6643s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6660s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_513] 0 - 0.98
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_772] 0 - 0.39
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1562] 1 True 14.11
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.4318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.11156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.11310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.11357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.11424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.11485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.11526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.11582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.11621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.11653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.11707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.11739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.11787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.11860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.11901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.11942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13108s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13115s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1956] 1 True 16.39
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== [TIDL Import] WARNING: Resize layer - with 'align_corners' coordinate_transformation_mode is not optimal The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.275s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3207s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3219s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= [TIDL Import] WARNING: Resize layer - with 'align_corners' coordinate_transformation_mode is not optimal ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 526912269 bytes MEM: Free's : 26 free's of 526912269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1801] 0 - 0.32
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1753] 0 - 0.34
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1565] 0 - 0.33
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1563] 0 - 0.38
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1474] 0 - 0.39
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1149] 0 - 0.45
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_974] 0 - 0.49
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_448] 0 - 0.30
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1224] 0 - 0.29
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_474] 0 - 0.31
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1357] 1 True 14.33
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.253s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3285s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3302s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1632] 0 - 1.07
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_557] 0 - 0.35
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_864] 0 - 0.33
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1416] 0 - 0.34
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1920] 0 - 0.42
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_145] 0 - 1.25
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1513] 1 True 10.95
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.473s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6789s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6810s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1842] 0 - 0.39
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1970] 0 - 0.39
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_674] 0 - 0.49
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1578] 0 - 16.88
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1761] 0 - 0.78
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_212] 0 - 0.52
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_711] 0 - 0.41
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1686] 1 True 13.84
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.369s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5376s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5383s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 99901277 bytes MEM: Free's : 26 free's of 99901277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_6] 0 - 1.63
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1202] 0 - 0.35
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1497] 0 - 0.79
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_103] 0 - 1.92
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_193] 0 - 0.93
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1846] 0 - 0.49
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1764] 0 - 0.32
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_332] 0 - 0.38
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_707] 1 True 15.74
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.428s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8261s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8287s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54701421 bytes MEM: Free's : 26 free's of 54701421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1803] 0 - 0.40
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1963] 1 True 13.34
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.400s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6122s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6137s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1023] 0 - 0.38
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1312] 0 - 1.06
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_143] 0 - 0.55
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_593] 0 - 0.42
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1689] 0 - 0.35
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_265] 1 True 11.98
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.227s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2732s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2741s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_877] 0 - 0.47
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1889] 0 - 0.38
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_613] 1 True 14.08
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.407s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6918s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6936s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1710] 0 - 0.53
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1592] 1 True 14.51
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.343s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3222s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3232s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_363] 0 - 0.39
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1527] 0 - 0.64
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1752] 0 - 0.64
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_252] 1 True 13.59
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.358s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3156s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3169s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_692] 0 - 0.30
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1815] 0 - 0.60
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1144] 0 - 0.61
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_724] 1 True 13.52
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.237s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2761s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2772s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_413] 0 - 0.34
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1287] 0 - 0.32
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1091] 1 True 11.74
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.354s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4682s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4690s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1979] 0 - 0.47
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1253] 0 - 0.39
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_314] 0 - 0.45
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_416] 1 True 11.86
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'round_prefer_floor' nearest mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4887s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4895s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_228] 0 - 0.74
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_397] 0 - 0.31
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_323] 0 - 0.64
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_130] 1 True 16.03
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.433s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7756s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7775s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1232] 0 - 6.59
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1749] 0 - 0.32
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_760] 0 - 0.38
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_633] 0 - 0.32
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_874] 0 - 0.25
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1553] 1 True 16.16
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7167s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7183s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1967] 1 True 14.66
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.204s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6846s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6858s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_462] 0 - 0.46
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1278] 0 - 0.40
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1904] 0 - 0.35
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1703] 1 True 9.31
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.228s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7714s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7720s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_627] 0 - 0.34
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_287] 0 - 0.24
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_688] 1 True 14.97
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.208s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2061s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2065s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1217] 0 - 0.34
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_562] 1 True 21.55
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.335s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6608s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6618s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 788633021 bytes MEM: Free's : 26 free's of 788633021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1857] 0 - 0.51
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_823] 0 - 0.40
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_293] 1 True 14.73
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.301s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4398s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4408s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 157895181 bytes MEM: Free's : 26 free's of 157895181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1065] 1 True 12.32
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.446s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5436s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5450s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_953] 0 - 0.57
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_697] 0 - 0.36
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_673] 0 - 0.30
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_958] 0 - 0.39
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1086] 0 - 0.64
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1844] 0 - 0.46
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1622] 0 - 0.30
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1302] 0 - 0.81
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1122] 0 - 23.71
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1075] 0 - 0.37
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_960] 0 - 0.64
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_392] 0 - 0.28
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_154] 0 - 0.60
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_233] 0 - 0.30
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_451] 0 - 0.30
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1029] 0 - 0.22
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1747] 0 - 2.24
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1581] 0 - 0.37
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1957] 0 - 0.46
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1063] 0 - 0.40
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1583] 0 - 0.44
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1349] 0 - 0.34
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1314] 0 - 0.29
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1388] 0 - 0.30
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_843] 0 - 0.40
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1322] 0 - 0.30
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1860] 0 - 0.89
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_703] 0 - 0.33
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_656] 0 - 0.86
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1789] 0 - 0.29
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_439] 0 - 0.30
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_908] 0 - 0.33
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_461] 0 - 0.31
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_27] 0 - 0.39
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_188] 1 True 13.30
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.477s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.11905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14136s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14148s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1366] 0 - 0.28
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1557] 0 - 0.23
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_279] 0 - 0.27
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_729] 0 - 2.50
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_890] 0 - 0.29
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_687] 0 - 0.41
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1981] 0 - 0.73
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_647] 0 - 0.33
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1270] 0 - 0.37
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1659] 1 True 17.17
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.153s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1855s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1860s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1480] 0 - 0.33
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_895] 0 - 0.37
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1279] 0 - 0.29
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1137] 1 True 8.90
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.458s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7897s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7922s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1780] 0 - 0.38
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1281] 0 - 0.37
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1079] 0 - 0.24
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_645] 0 - 0.55
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1343] 1 True 12.91
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.492s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8097s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8126s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54701421 bytes MEM: Free's : 26 free's of 54701421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_281] 0 - 0.45
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_918] 0 - 0.32
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1823] 1 True 12.87
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.474s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7441s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7454s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_966] 0 - 0.27
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1537] 0 - 0.39
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_128] 1 True 11.92
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.535s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8935s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8959s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1652] 0 - 0.22
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1162] 0 - 0.24
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1989] 0 - 0.30
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_816] 0 - 0.40
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1706] 0 - 0.69
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1365] 1 True 12.70
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5824s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5840s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1822] 0 - 0.41
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_438] 0 - 0.76
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1201] 0 - 0.65
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_197] 0 - 0.31
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_989] 0 - 0.73
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_979] 0 - 2.16
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_658] 0 - 0.38
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_663] 0 - 0.26
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1262] 1 True 14.04
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.226s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3076s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3089s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1845] 0 - 1.35
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_24] 0 - 0.31
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_710] 0 - 0.36
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1017] 1 True 13.85
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.383s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6066s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6084s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1164] 0 - 0.28
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1724] 0 - 1.60
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_101] 0 - 0.53
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1475] 0 - 0.34
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1414] 0 - 0.29
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_845] 0 - 0.38
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_126] 0 - 0.48
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_669] 0 - 0.33
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1502] 0 - 2.30
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_211] 0 - 0.39
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_349] 1 True 14.33
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.425s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6318s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6341s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_127] 0 - 0.30
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_719] 0 - 1.04
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1045] 0 - 0.90
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_906] 1 True 12.27
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.367s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6653s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6671s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1441] 0 - 0.93
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_748] 1 True 14.64
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.315s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4911s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4925s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1770] 1 True 12.32
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.358s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5355s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5370s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_994] 0 - 0.30
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_689] 1 True 15.41
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.192s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1869s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1873s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_591] 0 - 0.43
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_404] 0 - 0.31
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1269] 1 True 12.51
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.371s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5557s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5569s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1735] 0 - 0.37
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1532] 1 True 19.44
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.367s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5492s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5507s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 526912269 bytes MEM: Free's : 26 free's of 526912269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1369] 0 - 0.45
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_931] 0 - 0.44
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1107] 0 - 0.34
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1640] 0 - 0.38
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1534] 0 - 0.52
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_189] 0 - 0.81
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_998] 0 - 0.45
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1188] 0 - 0.27
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_429] 0 - 0.30
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1551] 0 - 0.33
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1944] 0 - 0.55
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_315] 0 - 0.35
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_369] 0 - 0.43
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1473] 0 - 0.38
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_993] 1 True 14.53
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.420s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7046s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7065s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_263] 0 - 0.30
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_213] 1 True 11.78
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.223s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2595s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2604s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 159042613 bytes MEM: Free's : 26 free's of 159042613 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_651] 0 - 0.40
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1372] 1 True 12.10
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.407s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6402s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6416s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_58] 1 True 9.34
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.520s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6369s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6382s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1512] 0 - 0.43
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_119] 0 - 0.40
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1389] 0 - 0.42
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1667] 0 - 0.34
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_920] 0 - 8.55
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_334] 0 - 0.42
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1402] 1 True 14.09
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.414s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7339s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7361s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_830] 0 - 5.46
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_826] 0 - 0.32
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1463] 0 - 0.66
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1538] 0 - 0.34
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1121] 1 True 13.41
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.406s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5382s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5397s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_41] 0 - 0.41
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_598] 0 - 0.46
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_272] 0 - 0.37
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_553] 0 - 0.48
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_871] 0 - 0.30
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_644] 0 - 0.26
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1400] 0 - 0.31
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1074] 0 - 0.60
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_231] 0 - 0.35
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_278] 1 True 12.76
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.335s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3981s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3995s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1717] 0 - 0.40
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1919] 1 True 13.11
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.297s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2979s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2991s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1226] 0 - 0.22
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1285] 1 True 14.41
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.400s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5559s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5575s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1530] 0 - 0.32
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_344] 0 - 0.38
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1996] 0 - 0.34
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_493] 0 - 0.31
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1277] 1 True 12.36
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.326s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3457s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3470s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_339] 0 - 0.27
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1827] 0 - 0.36
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1066] 0 - 0.37
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1142] 1 True 15.14
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.379s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9091s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9098s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 247024861 bytes MEM: Free's : 26 free's of 247024861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_276] 1 True 15.33
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.401s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7187s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7202s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_85] 0 - 0.65
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1738] 0 - 0.32
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1176] 0 - 0.27
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_677] 0 - 0.51
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_89] 0 - 1.28
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1223] 0 - 0.59
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_248] 0 - 0.30
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_358] 0 - 0.33
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_423] 0 - 0.27
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_62] 0 - 0.30
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_340] 0 - 0.31
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_409] 0 - 0.27
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_540] 1 True 14.32
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.401s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6314s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6333s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1171] 1 True 11.76
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8012s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8034s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_137] 0 - 0.25
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_207] 0 - 0.32
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1930] 1 True 14.89
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.456s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9901s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9909s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_415] 1 True 13.70
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== [TIDL Import] WARNING: Resize layer - with 'align_corners' coordinate_transformation_mode is not optimal The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.373s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6447s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6459s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= [TIDL Import] WARNING: Resize layer - with 'align_corners' coordinate_transformation_mode is not optimal ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 247024861 bytes MEM: Free's : 26 free's of 247024861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1438] 0 - 0.38
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_848] 0 - 0.80
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_370] 1 True 13.09
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'round_prefer_floor' nearest mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.339s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8731s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8741s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1612] 0 - 1.06
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_701] 0 - 0.32
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_862] 0 - 1.25
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_31] 0 - 0.31
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_109] 0 - 0.45
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_901] 0 - 0.31
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1974] 0 - 0.28
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_297] 0 - 0.31
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_22] 0 - 0.32
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1771] 0 - 0.36
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1124] 0 - 0.31
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1112] 0 - 1.12
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_480] 0 - 0.30
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1340] 1 True 14.15
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.420s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7754s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7775s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_934] 0 - 1.06
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1681] 0 - 0.30
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1511] 0 - 0.38
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_725] 0 - 1.52
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1843] 0 - 1.14
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_739] 0 - 0.36
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1574] 0 - 0.35
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_69] 0 - 0.67
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_326] 0 - 0.51
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_964] 0 - 0.47
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_682] 0 - 0.42
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1875] 0 - 0.64
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_702] 1 True 17.35
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.370s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5657s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5667s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1568] 1 True 13.58
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.497s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10072s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10083s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18823909 bytes MEM: Free's : 26 free's of 18823909 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_768] 1 True 11.97
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.255s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2509s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2521s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_885] 0 - 0.26
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_879] 0 - 0.22
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1864] 0 - 0.32
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_965] 1 True 16.09
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.186s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2323s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2330s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_754] 1 True 20.82
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4235s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4243s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 531413365 bytes MEM: Free's : 26 free's of 531413365 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1977] 0 - 0.35
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1650] 0 - 0.29
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_470] 0 - 0.65
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_364] 0 - 0.39
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1036] 0 - 0.40
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_150] 1 True 14.95
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.277s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2137s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2143s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 355628493 bytes MEM: Free's : 26 free's of 355628493 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1244] 0 - 0.47
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_53] 0 - 0.40
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_274] 0 - 0.53
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_842] 0 - 0.43
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_766] 0 - 0.53
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_928] 1 True 15.27
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.254s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2712s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2721s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1888] 0 - 0.42
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1629] 0 - 0.75
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1983] 0 - 0.50
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_720] 0 - 0.96
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_566] 0 - 0.44
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_545] 0 - 0.39
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_414] 0 - 0.38
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1384] 0 - 0.42
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1212] 0 - 0.33
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_977] 0 - 0.34
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_292] 0 - 0.36
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1794] 0 - 0.95
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1061] 0 - 0.79
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1836] 0 - 0.31
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_581] 0 - 0.49
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_585] 0 - 0.64
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_595] 0 - 1.05
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1111] 0 - 8.22
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1218] 1 True 11.55
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.326s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3276s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3286s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1577] 0 - 0.38
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1385] 0 - 0.34
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1945] 0 - 0.60
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_536] 0 - 15.70
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1535] 0 - 1.14
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_64] 0 - 0.38
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_752] 1 True 14.76
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.406s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4262s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4272s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_712] 0 - 0.51
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_298] 0 - 0.44
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_623] 0 - 0.44
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_433] 0 - 0.34
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_659] 1 True 12.76
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.232s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3049s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3056s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_683] 0 - 0.32
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1943] 0 - 5.33
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1442] 0 - 0.44
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_156] 0 - 0.50
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1499] 0 - 0.33
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_905] 0 - 0.33
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_437] 1 True 13.84
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.433s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8151s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8168s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_232] 0 - 0.59
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_741] 0 - 0.39
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1141] 0 - 0.73
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_872] 1 True 16.00
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.368s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5758s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5770s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_134] 1 True 12.13
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.371s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5588s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5607s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1566] 0 - 0.28
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1671] 1 True 12.16
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1240s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4013s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4021s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24289117 bytes MEM: Free's : 26 free's of 24289117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_898] 0 - 0.35
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1852] 0 - 0.34
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1910] 0 - 0.52
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1089] 0 - 0.45
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1420] 0 - 0.72
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1187] 0 - 0.38
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1649] 1 True 13.17
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.305s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3645s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3655s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19217125 bytes MEM: Free's : 26 free's of 19217125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_869] 0 - 0.36
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_133] 0 - 0.71
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1925] 0 - 0.25
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1315] 0 - 0.44
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_484] 0 - 0.47
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_759] 0 - 0.38
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_68] 0 - 0.35
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_957] 0 - 0.66
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1955] 1 True 15.00
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.415s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6776s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6798s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_442] 1 True 12.76
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.352s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12192s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12208s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_346] 0 - 0.28
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1524] 1 True 12.28
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7976s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7994s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1666] 0 - 0.36
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1647] 0 - 0.52
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1016] 0 - 0.43
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_141] 0 - 0.33
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1643] 0 - 0.31
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_857] 0 - 0.56
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_561] 0 - 0.26
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_291] 1 True 16.63
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.252s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10278s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10286s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_61] 0 - 0.33
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1813] 0 - 1.36
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_924] 0 - 1.11
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_534] 1 True 15.31
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.539s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7633s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7654s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1468] 0 - 0.76
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1132] 0 - 1.17
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1134] 0 - 0.31
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_665] 0 - 0.45
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1820] 0 - 1.19
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1598] 0 - 0.86
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1975] 0 - 0.38
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_543] 0 - 0.64
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1520] 0 - 0.32
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1427] 0 - 0.33
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1663] 0 - 0.36
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_306] 1 True 13.07
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.436s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6841s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6856s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_642] 0 - 1.34
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1009] 0 - 0.30
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_427] 0 - 0.34
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1117] 0 - 0.39
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_685] 0 - 0.33
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1362] 0 - 1.44
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_589] 0 - 0.40
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1653] 1 True 11.54
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3654s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3670s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1098] 0 - 0.45
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_619] 0 - 0.34
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1986] 0 - 0.33
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_83] 0 - 1.31
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_343] 0 - 0.43
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1938] 0 - 0.35
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_815] 0 - 0.27
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1444] 0 - 0.33
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_847] 0 - 0.47
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1308] 1 True 12.82
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.220s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2323s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2337s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_919] 0 - 0.33
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_762] 0 - 0.55
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1297] 0 - 0.45
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1433] 0 - 0.35
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_694] 0 - 0.31
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_162] 0 - 0.28
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_882] 0 - 0.38
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_932] 0 - 0.37
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_832] 1 True 16.06
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.505s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9080s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9105s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_184] 0 - 0.40
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1368] 0 - 0.37
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1215] 0 - 0.72
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_761] 0 - 0.64
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1406] 0 - 0.68
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_714] 0 - 0.29
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_222] 1 True 10.34
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'round_prefer_floor' nearest mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.436s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6997s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7023s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_587] 1 True 15.49
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.445s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7810s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7837s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 88037261 bytes MEM: Free's : 26 free's of 88037261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1539] 0 - 0.38
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_408] 0 - 0.45
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1569] 0 - 0.35
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1265] 0 - 0.43
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_615] 1 True 17.11
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.512s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7895s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7921s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24289117 bytes MEM: Free's : 26 free's of 24289117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1325] 0 - 0.52
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1264] 0 - 0.36
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_229] 1 True 14.50
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.464s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6486s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6511s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_806] 0 - 0.98
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1800] 0 - 0.41
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1291] 0 - 0.53
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_855] 1 True 11.06
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.501s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7472s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7496s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_238] 0 - 0.29
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_405] 0 - 0.26
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1178] 0 - 0.48
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_35] 0 - 0.40
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1154] 0 - 0.67
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1108] 0 - 1.02
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1759] 0 - 0.35
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1829] 0 - 0.29
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1411] 0 - 0.39
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_505] 0 - 0.58
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_913] 0 - 0.42
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1210] 0 - 0.44
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_853] 0 - 0.41
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_769] 0 - 0.32
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1900] 0 - 0.51
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_347] 0 - 0.68
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1276] 0 - 0.52
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1948] 0 - 0.31
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1928] 1 True 20.37
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.234s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2335s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2341s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 531413365 bytes MEM: Free's : 26 free's of 531413365 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1040] 0 - 0.32
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_790] 1 True 13.57
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.452s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6982s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7002s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_333] 0 - 0.31
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1677] 1 True 16.25
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== [TIDL Import] WARNING: Resize layer - with 'align_corners' coordinate_transformation_mode is not optimal The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.283s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3464s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3472s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= [TIDL Import] WARNING: Resize layer - with 'align_corners' coordinate_transformation_mode is not optimal ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19217125 bytes MEM: Free's : 26 free's of 19217125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1913] 0 - 0.60
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1350] 0 - 1.33
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_666] 0 - 0.34
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1596] 0 - 0.33
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_131] 0 - 0.32
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1762] 1 True 15.27
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.423s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9903s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9932s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 89769857 bytes MEM: Free's : 26 free's of 89769857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1272] 1 True 12.79
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.398s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6723s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6741s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_526] 0 - 0.45
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_466] 0 - 0.38
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1885] 0 - 0.37
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_173] 0 - 0.29
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1760] 0 - 1.10
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_303] 0 - 2.59
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_239] 0 - 0.54
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_425] 0 - 0.34
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_568] 1 True 12.74
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.259s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2565s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2576s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 89769857 bytes MEM: Free's : 26 free's of 89769857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_187] 0 - 0.38
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1552] 1 True 12.29
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.483s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7652s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7672s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_186] 0 - 0.37
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1082] 0 - 0.45
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1934] 0 - 0.77
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1949] 0 - 0.33
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_620] 0 - 0.29
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1199] 0 - 0.38
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_75] 1 True 19.22
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5499s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5522s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1561] 0 - 1.22
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_770] 0 - 0.37
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_657] 0 - 0.30
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_203] 0 - 0.34
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1958] 0 - 0.35
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_226] 0 - 0.42
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_602] 0 - 0.87
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1456] 0 - 1.08
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_636] 1 True 18.13
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.418s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6962s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6986s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19217125 bytes MEM: Free's : 26 free's of 19217125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_116] 0 - 0.43
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_668] 0 - 0.37
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_251] 1 True 16.55
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4359s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4372s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_224] 1 True 22.61
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.423s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6805s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6837s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 526912269 bytes MEM: Free's : 26 free's of 526912269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1165] 0 - 0.37
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_473] 0 - 0.63
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_508] 1 True 22.81
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.243s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3093s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3100s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54701421 bytes MEM: Free's : 26 free's of 54701421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1849] 0 - 0.81
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1437] 0 - 0.42
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1358] 1 True 15.29
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.288s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3133s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3146s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 37705613 bytes MEM: Free's : 26 free's of 37705613 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_328] 1 True 10.95
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.370s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5221s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5237s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1907] 0 - 3.42
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_744] 0 - 0.56
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_284] 0 - 1.89
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1051] 0 - 1.08
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_935] 1 True 13.40
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.281s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2341s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2351s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_721] 0 - 0.35
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_909] 0 - 0.31
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_301] 1 True 17.75
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.436s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6638s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6653s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_10] 0 - 0.34
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_482] 1 True 12.45
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.396s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6054s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6064s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_50] 0 - 0.36
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_996] 0 - 0.53
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1241] 1 True 14.81
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.244s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2747s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2755s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 88037261 bytes MEM: Free's : 26 free's of 88037261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_230] 0 - 0.34
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1038] 0 - 0.65
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1591] 0 - 0.38
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_833] 1 True 15.38
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.403s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6165s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6180s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_205] 0 - 0.68
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_167] 0 - 0.42
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_440] 0 - 0.42
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1531] 0 - 0.46
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_412] 0 - 0.78
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_378] 0 - 0.43
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_883] 1 True 14.84
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== [TIDL Import] WARNING: Resize layer - with 'align_corners' coordinate_transformation_mode is not optimal The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.236s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3001s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3006s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= [TIDL Import] WARNING: Resize layer - with 'align_corners' coordinate_transformation_mode is not optimal ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 89769857 bytes MEM: Free's : 26 free's of 89769857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_472] 0 - 0.34
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_100] 0 - 8.29
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1718] 1 True 13.55
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.274s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2930s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2940s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1094] 1 True 16.50
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.237s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2934s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2944s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 278513537 bytes MEM: Free's : 26 free's of 278513537 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_155] 1 True 15.60
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.315s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2965s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2976s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 531413365 bytes MEM: Free's : 26 free's of 531413365 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1150] 0 - 0.63
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_715] 0 - 0.35
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_444] 0 - 0.42
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_60] 0 - 0.44
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_250] 0 - 0.99
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_570] 0 - 0.49
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_880] 0 - 0.37
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_33] 0 - 0.53
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1240] 0 - 0.30
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_888] 0 - 2.37
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_835] 0 - 0.40
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_525] 1 True 12.17
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.412s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6053s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6063s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_455] 1 True 12.51
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.221s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2978s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2984s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1713] 0 - 0.30
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_245] 1 True 11.00
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.276s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2494s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2502s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1804] 0 - 0.46
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1624] 1 True 14.89
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.259s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2226s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2239s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 526912269 bytes MEM: Free's : 26 free's of 526912269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1505] 0 - 0.38
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1828] 0 - 0.68
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_37] 0 - 0.49
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_777] 0 - 0.48
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_196] 0 - 0.33
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_271] 0 - 0.43
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_431] 0 - 0.40
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1936] 1 True 14.41
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.552s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5839s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5856s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1627] 0 - 0.63
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1447] 0 - 0.25
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_256] 1 True 8.68
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4567s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4574s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1001] 0 - 0.34
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1257] 0 - 0.34
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_521] 0 - 0.38
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1390] 1 True 10.95
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.345s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6075s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6086s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1151] 1 True 8.97
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.142s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1722s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1727s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_383] 0 - 0.29
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1454] 0 - 0.41
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1973] 0 - 0.39
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_142] 0 - 0.39
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_90] 0 - 0.38
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_270] 0 - 0.26
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_219] 1 True 17.22
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.441s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8131s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8154s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20938973 bytes MEM: Free's : 26 free's of 20938973 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_172] 0 - 0.78
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_512] 0 - 0.67
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_445] 0 - 0.35
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_121] 0 - 0.66
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_96] 0 - 0.37
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_44] 0 - 0.32
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_452] 0 - 0.24
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_559] 0 - 0.38
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1064] 0 - 0.31
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_277] 0 - 0.38
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_803] 0 - 1.99
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1377] 0 - 0.20
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_558] 1 True 11.89
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4208s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4221s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_300] 0 - 0.59
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1496] 0 - 3.90
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1070] 0 - 0.31
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_709] 0 - 0.84
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_381] 0 - 0.30
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_635] 1 True 11.27
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'round_prefer_floor' nearest mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.444s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6905s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6926s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1263] 0 - 0.82
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1840] 0 - 1.68
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_962] 0 - 0.32
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1588] 0 - 0.43
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1638] 0 - 0.28
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1298] 0 - 0.21
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1455] 0 - 0.84
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_322] 1 True 17.78
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.381s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5836s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5847s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 37705613 bytes MEM: Free's : 26 free's of 37705613 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1988] 0 - 0.33
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1796] 0 - 4.24
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1404] 0 - 0.55
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_157] 0 - 0.26
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_313] 0 - 0.29
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_510] 1 True 15.67
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.269s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3454s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3465s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_21] 0 - 0.33
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1460] 0 - 0.45
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_827] 0 - 0.53
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_810] 0 - 0.59
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1998] 0 - 0.66
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1997] 0 - 0.49
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1763] 0 - 0.26
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_583] 0 - 0.41
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_262] 0 - 0.50
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1906] 0 - 0.33
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1256] 0 - 0.30
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_91] 0 - 1.55
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_286] 0 - 0.29
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1341] 0 - 0.23
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_740] 1 True 15.12
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.266s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3347s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3352s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1407] 0 - 0.36
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_185] 0 - 0.28
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_940] 0 - 0.31
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1485] 0 - 0.30
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1729] 0 - 0.44
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_951] 0 - 0.69
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_329] 0 - 0.24
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_866] 0 - 1.44
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1560] 0 - 0.63
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1220] 0 - 0.32
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1575] 0 - 0.28
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_290] 1 True 14.68
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.375s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6552s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6569s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1113] 0 - 1.08
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_537] 0 - 0.38
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1032] 0 - 0.60
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1757] 0 - 0.31
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_755] 0 - 0.36
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1504] 0 - 0.26
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_454] 0 - 0.60
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1247] 0 - 0.43
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_939] 0 - 0.60
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1661] 0 - 0.33
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_168] 0 - 0.32
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_652] 0 - 0.32
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1030] 0 - 0.27
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_402] 1 True 13.36
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.543s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9054s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9078s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1682] 0 - 0.66
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1095] 0 - 0.65
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_12] 1 True 16.78
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.235s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10101s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10108s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1902] 0 - 0.36
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1363] 0 - 0.57
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1680] 1 True 14.46
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.271s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4440s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4448s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1022] 0 - 1.02
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1] 1 True 15.19
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.193s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4227s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4235s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1664] 0 - 0.39
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1436] 0 - 0.38
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1068] 0 - 0.31
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1153] 0 - 0.32
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1251] 1 True 13.94
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.411s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6915s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6931s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1352] 0 - 0.43
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1730] 0 - 0.40
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_818] 1 True 12.60
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.432s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7647s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7665s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_199] 1 True 12.45
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.482s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6814s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6834s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_161] 0 - 0.84
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_216] 1 True 13.34
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.237s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1924s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1930s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_676] 0 - 0.27
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1282] 1 True 17.04
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7194s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7216s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1003] 1 True 11.75
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.432s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4959s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4973s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_107] 1 True 15.37
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.456s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6685s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6700s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_49] 0 - 0.36
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_55] 1 True 17.21
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.156s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6851s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6858s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 204471997 bytes MEM: Free's : 26 free's of 204471997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1559] 0 - 0.39
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_780] 0 - 0.90
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_789] 0 - 1.07
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1172] 0 - 0.42
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_371] 1 True 10.96
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.320s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4941s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4946s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1641] 0 - 0.53
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_192] 0 - 0.35
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_295] 0 - 0.33
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_549] 0 - 0.35
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1317] 1 True 22.48
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7609s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7630s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 1096662549 bytes MEM: Free's : 26 free's of 1096662549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_375] 0 - 0.35
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_804] 0 - 0.45
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1190] 1 True 16.06
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.245s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3743s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3750s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 89769857 bytes MEM: Free's : 26 free's of 89769857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1422] 0 - 0.33
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_66] 1 True 10.77
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.240s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8922s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8931s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24289117 bytes MEM: Free's : 26 free's of 24289117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_509] 1 True 14.97
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.418s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5810s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5832s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 103007693 bytes MEM: Free's : 26 free's of 103007693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_368] 0 - 0.33
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_606] 0 - 0.18
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1328] 0 - 0.26
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1662] 0 - 0.26
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1320] 0 - 0.49
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_319] 0 - 0.25
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_999] 0 - 0.22
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1995] 1 True 18.41
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3117s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3131s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 526912269 bytes MEM: Free's : 26 free's of 526912269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_160] 1 True 11.92
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.277s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3044s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3055s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_426] 0 - 0.25
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_531] 1 True 10.45
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.489s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8188s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8216s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_775] 0 - 0.23
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_889] 0 - 0.50
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1962] 0 - 0.37
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1380] 0 - 0.50
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_491] 0 - 0.24
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_190] 0 - 0.57
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1816] 1 True 15.53
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6645s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6659s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1169] 0 - 0.31
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_503] 0 - 0.26
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_504] 1 True 17.58
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.393s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4703s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4715s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1992] 0 - 0.31
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1487] 0 - 0.70
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1440] 0 - 0.67
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_179] 1 True 13.46
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.479s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11213s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11230s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1255] 0 - 2.82
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1408] 0 - 0.65
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1933] 0 - 0.29
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1087] 0 - 0.41
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_728] 0 - 0.33
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1586] 0 - 0.81
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_111] 0 - 0.52
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1139] 0 - 0.39
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_355] 1 True 11.08
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.498s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9229s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9258s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_542] 1 True 18.03
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.438s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7592s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7617s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1695] 0 - 0.36
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_235] 0 - 1.93
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_574] 1 True 14.46
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.475s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7908s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7929s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21100333 bytes MEM: Free's : 26 free's of 21100333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_176] 0 - 2.63
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_533] 1 True 13.39
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.425s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7434s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7450s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21100333 bytes MEM: Free's : 26 free's of 21100333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_341] 0 - 0.55
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1429] 0 - 3.77
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_195] 0 - 0.99
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1288] 1 True 14.50
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.475s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6976s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6990s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27391789 bytes MEM: Free's : 26 free's of 27391789 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1192] 0 - 0.57
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1367] 0 - 0.51
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1039] 0 - 0.45
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_149] 0 - 0.41
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1127] 0 - 0.33
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_47] 1 True 19.09
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.235s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2612s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2618s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_629] 1 True 18.01
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.406s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6108s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6124s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1042] 0 - 0.99
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1619] 0 - 0.41
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1786] 0 - 0.42
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1912] 1 True 17.63
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.344s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5080s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5097s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_716] 0 - 0.56
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1323] 1 True 18.65
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.468s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7974s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7994s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1863] 1 True 17.48
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.358s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5655s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5663s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1903] 0 - 0.38
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_733] 0 - 0.58
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_785] 0 - 0.51
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_54] 1 True 17.10
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.350s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4251s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4269s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 88037261 bytes MEM: Free's : 26 free's of 88037261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1951] 0 - 0.82
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_828] 0 - 0.74
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1509] 0 - 0.52
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1585] 0 - 0.57
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1081] 0 - 1.84
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1184] 0 - 0.36
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1170] 1 True 16.52
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.440s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7084s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7102s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_975] 0 - 0.75
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1186] 0 - 0.40
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1197] 0 - 0.35
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_630] 1 True 15.48
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.243s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2552s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2559s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1296] 0 - 0.40
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1623] 1 True 15.10
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.266s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2172s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2179s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_995] 1 True 15.17
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.366s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5329s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5337s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_450] 0 - 0.40
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1006] 0 - 0.39
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_225] 0 - 0.73
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_237] 0 - 0.52
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_661] 1 True 14.46
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.273s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3466s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3474s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_649] 0 - 0.64
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1382] 0 - 0.28
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1519] 0 - 0.51
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1847] 0 - 0.35
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_483] 0 - 0.38
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_459] 1 True 12.40
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.395s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6148s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6163s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_495] 0 - 0.78
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_959] 0 - 0.38
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1311] 0 - 0.42
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_365] 0 - 0.37
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1684] 1 True 17.45
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.221s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.10007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.10065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.10110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.10153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.10196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.10240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.10277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11708s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11719s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 531413365 bytes MEM: Free's : 26 free's of 531413365 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_821] 1 True 13.13
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.279s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3550s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3560s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_217] 0 - 0.30
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1138] 0 - 3.67
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_151] 0 - 1.83
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_693] 0 - 0.39
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1737] 0 - 0.76
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_938] 1 True 11.27
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.223s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3394s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3402s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_432] 1 True 14.92
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.481s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7295s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7319s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 204471997 bytes MEM: Free's : 26 free's of 204471997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_57] 0 - 0.28
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_910] 0 - 0.20
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_616] 0 - 0.97
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1378] 0 - 0.60
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1674] 0 - 0.31
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1779] 0 - 0.28
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1336] 1 True 11.89
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.239s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6391s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6397s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1338] 0 - 0.66
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_567] 0 - 0.31
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_302] 1 True 14.23
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.452s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7172s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7196s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 204471997 bytes MEM: Free's : 26 free's of 204471997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1249] 0 - 0.54
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_460] 0 - 0.26
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_522] 0 - 0.35
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1067] 0 - 0.32
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_846] 1 True 12.29
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.435s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7180s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7195s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1056] 1 True 11.65
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.548s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8598s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8622s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1214] 0 - 0.32
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1726] 0 - 0.54
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1482] 0 - 0.31
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_930] 1 True 12.64
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.287s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9954s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9966s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_916] 0 - 0.33
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_584] 0 - 0.28
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1660] 0 - 0.39
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1620] 0 - 0.39
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_481] 0 - 0.45
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_941] 1 True 14.27
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.252s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3005s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3013s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1848] 0 - 0.55
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_86] 0 - 0.27
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1685] 0 - 0.35
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_969] 0 - 0.27
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1688] 0 - 0.41
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1452] 1 True 10.48
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.282s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2765s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2777s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54701421 bytes MEM: Free's : 26 free's of 54701421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1449] 0 - 0.24
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_475] 0 - 0.26
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_784] 0 - 0.29
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_787] 0 - 0.38
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1917] 0 - 0.28
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1750] 0 - 0.48
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1093] 0 - 0.31
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_569] 0 - 0.57
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1371] 0 - 0.48
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1486] 0 - 0.57
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_310] 0 - 0.35
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1080] 1 True 10.91
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.129s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1674s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1678s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1083] 0 - 0.46
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1417] 1 True 14.19
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.269s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3451s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3459s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54701421 bytes MEM: Free's : 26 free's of 54701421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1376] 1 True 19.55
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.410s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6451s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6469s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 81271645 bytes MEM: Free's : 26 free's of 81271645 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_947] 0 - 0.29
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1166] 1 True 13.14
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.465s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7553s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7573s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_596] 0 - 0.52
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_955] 0 - 0.39
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_891] 0 - 0.38
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1915] 0 - 0.30
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_15] 1 True 14.59
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.184s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2051s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2057s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_631] 0 - 0.27
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1077] 0 - 0.42
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1617] 0 - 0.54
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1795] 0 - 0.38
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_605] 0 - 0.71
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_488] 0 - 0.27
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_348] 0 - 0.39
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1428] 0 - 0.39
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1424] 1 True 11.97
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.467s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7111s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7128s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1866] 0 - 1.73
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1880] 0 - 0.33
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1435] 0 - 0.56
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1161] 1 True 11.60
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'round_prefer_floor' nearest mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.279s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5624s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5636s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1159] 0 - 0.33
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_586] 0 - 0.45
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_902] 0 - 0.34
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_74] 0 - 0.28
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_990] 0 - 0.39
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_73] 0 - 0.78
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_361] 0 - 0.40
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1867] 0 - 0.37
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_742] 0 - 2.64
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_778] 0 - 0.31
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1200] 0 - 0.50
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1601] 0 - 0.38
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_153] 1 True 16.32
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.473s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6932s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6945s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24289117 bytes MEM: Free's : 26 free's of 24289117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1373] 0 - 0.34
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_961] 0 - 0.35
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1719] 0 - 0.97
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1811] 1 True 14.22
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.372s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4143s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4156s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_28] 1 True 19.57
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.448s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6439s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6453s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1381] 0 - 0.35
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1922] 1 True 11.96
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.237s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2301s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2308s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_384] 0 - 0.65
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1458] 0 - 0.35
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1490] 0 - 0.33
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1926] 0 - 0.64
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1008] 0 - 0.52
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_881] 0 - 0.74
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1227] 0 - 0.51
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_735] 0 - 0.59
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_200] 1 True 17.30
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.412s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6486s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6505s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_42] 1 True 14.02
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.479s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7456s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7476s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1697] 0 - 0.34
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1348] 0 - 0.34
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1616] 0 - 0.43
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_244] 0 - 0.35
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1010] 0 - 0.47
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1570] 0 - 1.71
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1395] 0 - 0.58
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_299] 0 - 0.31
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_351] 0 - 0.35
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_529] 0 - 0.26
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_511] 0 - 0.29
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_158] 0 - 0.63
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_612] 0 - 0.37
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1742] 0 - 0.37
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1415] 0 - 0.44
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_330] 0 - 0.44
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_708] 0 - 0.36
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1940] 0 - 0.80
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1024] 0 - 0.29
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1476] 1 True 13.65
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.412s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4304s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4314s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_138] 0 - 0.33
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1869] 0 - 0.41
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_655] 0 - 0.54
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1007] 1 True 14.57
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.477s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7730s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7748s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_793] 0 - 0.39
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1173] 0 - 0.51
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1102] 0 - 0.78
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1821] 1 True 15.21
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4880s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4890s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1182] 0 - 0.46
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_170] 1 True 19.29
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.398s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6064s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6075s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 526912269 bytes MEM: Free's : 26 free's of 526912269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1610] 0 - 0.28
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_353] 1 True 16.42
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8817s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8826s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_77] 0 - 0.65
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_717] 0 - 0.73
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1642] 0 - 0.45
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_214] 0 - 0.53
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1898] 0 - 0.41
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1026] 0 - 0.49
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1978] 1 True 13.52
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.427s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7088s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7108s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1434] 0 - 0.36
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1756] 0 - 0.32
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1792] 0 - 1.72
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1777] 0 - 0.51
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_316] 0 - 1.70
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_9] 0 - 0.54
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1275] 0 - 0.36
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_886] 0 - 0.64
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_147] 0 - 0.53
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1347] 0 - 0.32
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_988] 0 - 0.28
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1668] 0 - 0.79
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_753] 0 - 0.89
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1705] 1 True 13.81
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.203s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2207s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2216s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_56] 0 - 0.33
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1891] 0 - 0.32
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1330] 0 - 0.33
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1808] 0 - 0.41
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_563] 0 - 0.37
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_868] 1 True 12.49
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.429s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5870s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5882s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1775] 0 - 0.23
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_236] 0 - 0.58
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1060] 0 - 0.52
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1470] 1 True 12.81
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.394s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5765s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5779s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1461] 0 - 0.30
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_401] 0 - 0.33
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_257] 1 True 11.92
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.211s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2205s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2212s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1231] 0 - 0.22
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_464] 1 True 11.22
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.301s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4657s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4665s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 88037261 bytes MEM: Free's : 26 free's of 88037261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1152] 0 - 0.41
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1503] 0 - 0.40
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1034] 0 - 0.34
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1054] 0 - 0.87
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1203] 0 - 0.34
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_851] 0 - 0.43
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1872] 0 - 0.41
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_45] 0 - 0.46
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1410] 0 - 0.38
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_336] 0 - 0.52
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_535] 1 True 12.21
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7686s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7692s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1174] 0 - 0.43
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1856] 1 True 10.93
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.398s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6044s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6056s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1658] 0 - 0.36
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1135] 0 - 5.25
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1479] 0 - 0.35
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1507] 0 - 0.40
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_80] 0 - 0.39
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_807] 0 - 0.35
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_809] 0 - 0.36
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1704] 0 - 1.08
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1892] 0 - 0.63
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_120] 0 - 0.38
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1564] 1 True 16.85
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3517s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3530s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1334] 0 - 1.06
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1339] 0 - 1.11
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_730] 1 True 15.94
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.337s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4201s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4216s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_338] 0 - 0.33
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1280] 1 True 15.69
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3336s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3351s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54701421 bytes MEM: Free's : 26 free's of 54701421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_421] 0 - 0.41
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1819] 1 True 14.45
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.551s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10791s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10823s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1225] 1 True 16.60
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3136s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3160s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20938973 bytes MEM: Free's : 26 free's of 20938973 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_498] 0 - 0.36
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_749] 0 - 0.31
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_894] 0 - 0.73
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1208] 0 - 0.34
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1769] 0 - 0.45
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1439] 0 - 0.35
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_174] 0 - 0.37
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1167] 0 - 0.62
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_399] 0 - 0.31
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1887] 0 - 2.65
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_507] 0 - 0.32
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_514] 0 - 0.22
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1129] 0 - 3.60
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_178] 0 - 0.38
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1185] 0 - 0.31
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_398] 0 - 0.28
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1401] 0 - 0.26
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1500] 0 - 0.26
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_321] 0 - 0.25
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1651] 1 True 10.66
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3814s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3828s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_335] 0 - 1.21
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_385] 0 - 0.26
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_675] 0 - 0.35
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_492] 1 True 12.67
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.619s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4008s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4017s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1543] 0 - 0.28
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_182] 1 True 14.46
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.385s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5969s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5983s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1041] 1 True 12.59
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7279s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7288s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1613] 0 - 0.35
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1324] 0 - 0.30
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_518] 0 - 0.90
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_285] 0 - 0.29
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_691] 0 - 1.24
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_648] 0 - 0.25
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_393] 1 True 18.53
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3133s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3144s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 306286125 bytes MEM: Free's : 26 free's of 306286125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1798] 0 - 0.42
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1533] 1 True 14.44
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.340s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5480s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5492s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1646] 1 True 13.69
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.402s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7498s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7526s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_449] 0 - 0.73
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1972] 0 - 0.28
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_547] 0 - 0.29
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1118] 0 - 0.42
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1331] 1 True 11.89
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.483s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7342s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7362s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1472] 1 True 14.60
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2649s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2658s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1758] 0 - 0.37
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_734] 1 True 22.72
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.436s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7859s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7882s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 531413365 bytes MEM: Free's : 26 free's of 531413365 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1728] 1 True 12.80
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6702s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6721s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_834] 0 - 0.93
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1375] 0 - 2.39
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1432] 0 - 0.47
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1896] 0 - 1.02
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_670] 1 True 14.46
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5237s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5246s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54701421 bytes MEM: Free's : 26 free's of 54701421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_985] 0 - 0.40
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_497] 0 - 0.63
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_786] 0 - 0.45
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1954] 1 True 10.43
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.364s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5529s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5542s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_32] 0 - 3.28
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_13] 0 - 0.43
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1305] 1 True 12.89
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.271s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2340s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2348s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1238] 0 - 0.47
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1897] 0 - 0.63
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1645] 0 - 1.67
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1621] 0 - 0.69
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_443] 1 True 18.83
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.275s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4158s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4169s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 247024861 bytes MEM: Free's : 26 free's of 247024861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_573] 1 True 13.46
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.497s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6533s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6548s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_554] 0 - 0.58
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_541] 0 - 0.45
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1194] 0 - 0.86
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1515] 1 True 13.73
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.267s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2665s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2675s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_978] 0 - 0.41
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1654] 1 True 16.62
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.505s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6504s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6516s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_486] 0 - 0.61
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1084] 1 True 14.82
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.168s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2414s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2419s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1540] 0 - 0.45
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1546] 0 - 0.28
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1861] 0 - 0.92
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_923] 0 - 0.49
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1508] 0 - 0.57
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_805] 0 - 1.24
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_771] 0 - 0.45
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_607] 0 - 0.47
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1806] 0 - 0.40
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1691] 0 - 5.53
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_26] 0 - 0.62
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1831] 0 - 0.42
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1522] 1 True 13.57
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.533s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8554s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8572s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 69729469 bytes MEM: Free's : 26 free's of 69729469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1701] 0 - 0.33
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1364] 0 - 0.38
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1333] 0 - 0.42
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_453] 1 True 12.54
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.410s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6536s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6549s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 88037261 bytes MEM: Free's : 26 free's of 88037261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1878] 0 - 0.52
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1923] 0 - 0.32
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1501] 0 - 0.41
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_839] 0 - 0.49
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1103] 0 - 0.50
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_356] 0 - 0.46
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_954] 1 True 12.83
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.431s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7516s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7534s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1491] 0 - 0.34
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1115] 0 - 0.31
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_29] 0 - 2.39
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1971] 0 - 1.00
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_914] 0 - 0.82
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_46] 0 - 1.25
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_797] 1 True 10.69
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5944s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5949s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1830] 0 - 0.31
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_756] 1 True 26.40
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3448s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3462s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 965555093 bytes MEM: Free's : 26 free's of 965555093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_282] 0 - 0.29
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_971] 0 - 1.02
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_671] 0 - 2.38
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1345] 0 - 1.25
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_465] 0 - 0.32
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1739] 0 - 0.89
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_746] 1 True 19.52
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3842s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3854s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_621] 0 - 0.25
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_706] 0 - 4.79
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1959] 1 True 13.95
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.335s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4002s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4015s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_867] 0 - 0.50
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1521] 0 - 1.41
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1609] 1 True 15.35
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3661s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3674s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1702] 0 - 0.49
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1644] 0 - 0.45
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1313] 0 - 0.35
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_592] 1 True 16.81
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.454s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6358s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6375s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54701421 bytes MEM: Free's : 26 free's of 54701421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1133] 0 - 0.37
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_637] 0 - 0.37
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1405] 1 True 20.10
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.513s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7849s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7875s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 965555093 bytes MEM: Free's : 26 free's of 965555093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_382] 1 True 17.78
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.496s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7889s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7914s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19217125 bytes MEM: Free's : 26 free's of 19217125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_622] 0 - 0.38
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1329] 0 - 0.39
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1851] 1 True 16.48
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.554s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9095s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9118s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1850] 0 - 0.47
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1005] 0 - 2.38
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1720] 0 - 0.93
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1421] 0 - 0.42
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1838] 0 - 0.40
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_317] 1 True 15.73
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.303s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2756s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2770s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_14] 0 - 0.33
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_952] 0 - 0.38
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1409] 0 - 1.57
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1545] 0 - 0.54
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1990] 0 - 0.33
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_118] 0 - 0.37
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1605] 0 - 0.35
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1999] 0 - 0.34
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_4] 0 - 0.25
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1230] 0 - 2.74
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1055] 0 - 0.35
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_527] 1 True 14.69
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.217s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2027s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2033s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1784] 0 - 0.69
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1216] 1 True 13.96
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.498s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8443s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8466s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1510] 0 - 0.41
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1576] 0 - 0.26
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_548] 0 - 0.74
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1211] 0 - 0.38
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_576] 0 - 0.42
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1394] 0 - 0.31
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_594] 0 - 0.48
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_861] 0 - 0.40
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_209] 0 - 0.29
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1639] 0 - 0.47
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1773] 0 - 0.62
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1699] 0 - 0.31
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_865] 0 - 1.25
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1865] 1 True 12.73
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.373s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5987s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5999s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_124] 0 - 0.28
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_36] 0 - 0.44
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1751] 0 - 0.25
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1392] 0 - 0.28
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_467] 1 True 12.76
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5219s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5229s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1768] 0 - 0.40
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_601] 1 True 11.72
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.254s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3190s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3202s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1033] 0 - 0.32
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_948] 0 - 0.29
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1573] 0 - 0.68
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_391] 0 - 2.50
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1549] 0 - 0.26
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1599] 0 - 0.28
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_25] 1 True 13.81
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.295s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4344s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4352s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1950] 0 - 0.61
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_893] 0 - 0.58
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1450] 0 - 0.40
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1425] 1 True 13.06
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.387s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5519s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5533s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_897] 0 - 0.74
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_387] 0 - 0.48
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1245] 1 True 16.38
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.174s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4511s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4522s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1782] 1 True 10.63
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== [TIDL Import] WARNING: Resize layer - with 'align_corners' coordinate_transformation_mode is not optimal The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.214s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2637s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2644s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= [TIDL Import] WARNING: Resize layer - with 'align_corners' coordinate_transformation_mode is not optimal ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 37705613 bytes MEM: Free's : 26 free's of 37705613 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_860] 0 - 0.39
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1715] 1 True 15.85
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.347s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3788s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3799s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_249] 0 - 0.43
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1031] 0 - 0.46
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1163] 0 - 0.50
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1403] 0 - 1.31
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_129] 0 - 0.46
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_342] 0 - 0.53
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1319] 0 - 0.68
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1584] 0 - 2.04
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_70] 0 - 0.72
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1469] 0 - 0.74
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1360] 1 True 15.60
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.522s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7719s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7736s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_457] 1 True 15.06
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4892s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4901s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27391789 bytes MEM: Free's : 26 free's of 27391789 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1965] 0 - 4.51
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1968] 0 - 0.33
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_795] 1 True 14.85
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.432s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8944s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8967s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_844] 0 - 0.42
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_30] 1 True 13.28
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.272s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3633s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3644s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1344] 0 - 2.84
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1536] 0 - 0.45
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_970] 0 - 0.37
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_65] 1 True 12.45
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.398s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6435s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6451s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1426] 0 - 0.26
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1097] 1 True 13.23
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.366s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6752s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6774s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_215] 0 - 2.07
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1587] 0 - 0.89
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_377] 0 - 0.84
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1046] 1 True 13.10
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== [TIDL Import] WARNING: Resize layer - with 'align_corners' coordinate_transformation_mode is not optimal The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.420s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5775s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5790s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= [TIDL Import] WARNING: Resize layer - with 'align_corners' coordinate_transformation_mode is not optimal ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 159042613 bytes MEM: Free's : 26 free's of 159042613 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1386] 0 - 0.34
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1396] 0 - 0.75
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_104] 0 - 0.23
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_892] 1 True 14.56
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.377s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.10023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.10086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.10147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.10207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.10278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.10337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.10418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.10502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.11032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.11172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.11241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12734s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12756s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1057] 0 - 0.97
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_618] 0 - 0.33
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1883] 1 True 16.45
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.448s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6843s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6861s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1145] 0 - 0.35
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_164] 1 True 14.78
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.486s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6706s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6721s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1547] 0 - 0.40
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1678] 0 - 0.30
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1529] 1 True 16.99
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.240s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3020s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3034s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_367] 1 True 13.29
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.477s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7320s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7348s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1266] 0 - 0.32
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1785] 0 - 0.50
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_917] 1 True 12.75
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.470s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7557s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7578s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1301] 0 - 0.32
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1700] 0 - 0.40
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_102] 1 True 11.42
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3748s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3761s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_515] 0 - 1.08
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_246] 1 True 12.43
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.270s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4579s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4600s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1189] 0 - 0.47
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_501] 0 - 0.35
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1123] 0 - 0.39
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_765] 0 - 0.80
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_206] 0 - 0.38
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1157] 0 - 0.65
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1002] 0 - 0.39
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_588] 0 - 0.35
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1767] 1 True 23.32
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.467s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7232s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7249s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 788633021 bytes MEM: Free's : 26 free's of 788633021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1953] 0 - 0.46
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1423] 0 - 0.36
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_560] 0 - 0.33
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1290] 0 - 0.38
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1835] 0 - 0.37
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1131] 0 - 1.01
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1969] 0 - 1.24
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1895] 0 - 3.79
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_396] 0 - 0.60
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_476] 0 - 0.35
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1506] 1 True 18.49
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.379s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7592s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7611s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1595] 1 True 12.77
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.413s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7174s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7200s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_572] 0 - 1.80
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1541] 0 - 0.35
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1693] 1 True 13.85
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.449s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7609s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7631s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1239] 0 - 0.45
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_718] 0 - 0.37
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_92] 0 - 0.46
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_550] 0 - 0.53
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1431] 1 True 11.38
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.183s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1881s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1886s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_19] 0 - 0.40
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_929] 0 - 0.69
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_773] 0 - 0.34
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1877] 0 - 0.33
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_210] 1 True 20.57
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.525s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7290s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7309s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 355628493 bytes MEM: Free's : 26 free's of 355628493 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1709] 0 - 0.37
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1712] 1 True 19.32
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.215s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2180s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2191s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_327] 1 True 16.34
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.412s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6399s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6415s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_678] 0 - 0.52
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_555] 0 - 0.38
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1261] 0 - 0.39
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_471] 0 - 0.42
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1556] 0 - 0.42
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_253] 0 - 2.94
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_814] 0 - 0.52
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1905] 0 - 0.73
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_374] 1 True 14.66
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.544s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7597s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7614s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1464] 0 - 0.40
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_81] 0 - 0.36
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_411] 1 True 13.04
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.566s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8152s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8175s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1597] 1 True 17.39
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.443s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7265s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7282s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 88037261 bytes MEM: Free's : 26 free's of 88037261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_264] 0 - 0.48
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_359] 0 - 0.42
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1391] 0 - 0.31
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1593] 1 True 17.39
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== [TIDL Import] WARNING: Resize layer - with 'align_corners' coordinate_transformation_mode is not optimal The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.207s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1907s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1913s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= [TIDL Import] WARNING: Resize layer - with 'align_corners' coordinate_transformation_mode is not optimal ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 526912269 bytes MEM: Free's : 26 free's of 526912269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1555] 0 - 0.45
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_942] 0 - 0.55
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1383] 0 - 0.44
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1765] 0 - 0.30
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_788] 0 - 0.43
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_582] 0 - 0.35
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_125] 0 - 0.37
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1526] 0 - 0.34
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1120] 0 - 0.33
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1582] 0 - 0.42
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1309] 0 - 0.41
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1882] 1 True 12.18
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.489s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7624s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7644s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_259] 1 True 19.67
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.276s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2668s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2678s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 247024861 bytes MEM: Free's : 26 free's of 247024861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_171] 1 True 12.76
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6983s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7002s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1069] 0 - 0.27
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_67] 0 - 0.33
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_479] 0 - 0.29
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_808] 1 True 14.98
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.223s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3084s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3092s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_956] 1 True 12.67
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.461s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7585s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7611s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24289117 bytes MEM: Free's : 26 free's of 24289117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_943] 0 - 0.46
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_732] 0 - 0.68
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_7] 0 - 0.48
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_389] 0 - 0.39
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_234] 0 - 0.39
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_632] 0 - 0.34
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_967] 0 - 2.90
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_643] 0 - 0.25
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1884] 0 - 0.50
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_698] 0 - 0.34
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1980] 0 - 0.38
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1814] 0 - 0.36
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_305] 1 True 20.96
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.269s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3746s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3763s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 526912269 bytes MEM: Free's : 26 free's of 526912269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_824] 0 - 0.35
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1268] 0 - 0.33
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_357] 0 - 0.32
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1076] 0 - 0.50
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_394] 1 True 12.47
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.463s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7304s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7329s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 103007693 bytes MEM: Free's : 26 free's of 103007693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_524] 0 - 0.34
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1960] 0 - 0.30
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1284] 0 - 0.29
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1618] 0 - 0.35
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_794] 1 True 11.76
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.239s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3640s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3657s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1207] 1 True 12.91
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'round_prefer_floor' nearest mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3174s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3184s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1259] 1 True 13.93
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.400s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6214s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6232s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 54701421 bytes MEM: Free's : 26 free's of 54701421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1607] 0 - 0.34
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_115] 1 True 23.06
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3039s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3046s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 204471997 bytes MEM: Free's : 26 free's of 204471997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1916] 0 - 0.45
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_376] 0 - 0.43
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1493] 1 True 13.77
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.441s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6469s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6486s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1303] 1 True 15.02
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.260s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2349s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2359s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1293] 0 - 0.41
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1310] 0 - 0.57
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1221] 0 - 0.35
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1833] 0 - 0.66
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_903] 0 - 0.28
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_811] 0 - 0.44
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1890] 0 - 2.80
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1252] 0 - 0.40
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_747] 1 True 13.43
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3353s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3369s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_18] 0 - 0.31
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1043] 1 True 14.52
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.271s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2573s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2579s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1346] 1 True 14.41
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7665s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7682s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1941] 0 - 0.48
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1000] 1 True 11.91
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.260s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3544s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3557s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18823909 bytes MEM: Free's : 26 free's of 18823909 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1734] 0 - 0.32
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_140] 0 - 0.35
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_763] 0 - 2.51
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1412] 1 True 16.68
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3474s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3479s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1908] 0 - 0.36
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_946] 0 - 0.28
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_987] 0 - 0.30
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_175] 0 - 0.32
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1542] 1 True 17.36
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.531s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7877s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7903s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18823909 bytes MEM: Free's : 26 free's of 18823909 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1636] 0 - 0.28
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_500] 1 True 19.13
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.282s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2596s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2604s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21100333 bytes MEM: Free's : 26 free's of 21100333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1498] 0 - 0.51
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1707] 0 - 0.64
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_441] 1 True 16.28
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.532s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9515s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9540s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39034717 bytes MEM: Free's : 26 free's of 39034717 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_539] 1 True 17.57
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.461s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7653s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7673s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24289117 bytes MEM: Free's : 26 free's of 24289117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1101] 0 - 1.41
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1797] 0 - 0.42
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_152] 1 True 17.14
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.287s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3260s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3275s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_801] 1 True 11.70
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4326s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4335s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_791] 0 - 0.36
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1614] 0 - 0.50
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_144] 0 - 0.37
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1198] 0 - 0.27
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1606] 0 - 0.33
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_180] 0 - 0.33
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_992] 0 - 0.47
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1105] 1 True 13.59
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.360s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5521s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5531s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_640] 1 True 16.62
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.433s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6011s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6020s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_84] 1 True 16.47
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.441s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7447s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7464s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1744] 0 - 0.89
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1714] 0 - 0.63
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_422] 0 - 0.88
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1859] 0 - 0.43
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1128] 0 - 0.49
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_726] 0 - 0.38
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1937] 1 True 17.12
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.284s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3412s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3423s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1053] 1 True 16.91
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.373s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5879s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5901s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1634] 0 - 0.42
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1886] 0 - 0.44
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1219] 0 - 0.45
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_506] 0 - 0.33
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_603] 0 - 0.85
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1901] 1 True 13.18
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.393s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6601s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6618s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1090] 0 - 0.62
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1648] 0 - 0.42
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1492] 0 - 4.87
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_273] 0 - 0.48
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_887] 0 - 1.00
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_812] 1 True 12.59
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.236s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2278s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2286s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 37705613 bytes MEM: Free's : 26 free's of 37705613 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_799] 0 - 0.27
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_976] 0 - 0.78
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1911] 0 - 0.35
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1774] 0 - 0.35
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_159] 0 - 0.73
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_5] 0 - 0.34
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1630] 1 True 16.42
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.488s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9708s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9731s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1567] 0 - 0.45
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1342] 1 True 18.93
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.481s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6776s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6790s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1020] 0 - 0.41
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_108] 0 - 0.46
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_738] 0 - 0.46
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1873] 0 - 0.33
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_849] 1 True 14.43
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.308s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5222s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5235s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_986] 1 True 11.21
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.521s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7479s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7498s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_546] 1 True 12.48
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5259s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5264s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1294] 0 - 0.33
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_294] 0 - 0.42
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_646] 0 - 0.35
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_664] 1 True 14.62
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7544s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7565s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1465] 1 True 12.70
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3560s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3571s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 88037261 bytes MEM: Free's : 26 free's of 88037261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1398] 1 True 13.28
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6694s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6706s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1994] 0 - 0.37
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1335] 0 - 0.42
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_680] 0 - 0.44
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_165] 1 True 14.85
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== [TIDL Import] WARNING: Resize layer - with 'align_corners' coordinate_transformation_mode is not optimal The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.368s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5313s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5324s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= [TIDL Import] WARNING: Resize layer - with 'align_corners' coordinate_transformation_mode is not optimal ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 69729469 bytes MEM: Free's : 26 free's of 69729469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_751] 1 True 13.71
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.251s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2493s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2501s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1694] 1 True 13.86
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.400s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6388s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6406s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 69729469 bytes MEM: Free's : 26 free's of 69729469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1993] 0 - 0.45
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_105] 0 - 0.29
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1027] 0 - 0.41
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_779] 0 - 0.45
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1316] 0 - 0.32
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_859] 0 - 0.40
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1931] 1 True 12.92
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.505s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9133s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9162s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_148] 1 True 15.47
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.303s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3006s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3022s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1035] 0 - 0.28
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_2000] 0 - 0.69
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1746] 0 - 0.38
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_551] 0 - 0.41
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1858] 1 True 10.48
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.256s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2568s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2576s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_218] 1 True 17.72
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.241s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2219s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2231s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 89769857 bytes MEM: Free's : 26 free's of 89769857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1690] 0 - 0.27
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1306] 1 True 17.92
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.271s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2429s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2442s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1788] 0 - 0.48
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_201] 1 True 25.63
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.456s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6413s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6432s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 1096662549 bytes MEM: Free's : 26 free's of 1096662549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1106] 1 True 10.99
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3451s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3462s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1179] 0 - 0.32
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_436] 0 - 0.28
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1947] 1 True 16.58
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.414s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5501s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5514s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 355628493 bytes MEM: Free's : 26 free's of 355628493 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1572] 0 - 0.33
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1300] 0 - 0.44
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_722] 1 True 11.04
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4555s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4565s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1078] 0 - 0.48
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_16] 0 - 0.35
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_123] 0 - 0.96
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1745] 0 - 0.34
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1733] 0 - 1.09
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_223] 0 - 0.45
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_870] 1 True 14.07
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.272s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2452s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2467s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_638] 0 - 0.45
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1914] 0 - 0.35
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1918] 0 - 0.40
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_388] 0 - 0.25
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_704] 1 True 16.31
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.468s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8077s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8098s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1589] 0 - 0.33
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1119] 1 True 12.52
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.403s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6886s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6896s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1104] 0 - 0.33
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1868] 0 - 0.56
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1110] 0 - 0.34
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1810] 0 - 0.36
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_430] 0 - 0.44
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_624] 0 - 0.44
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_419] 0 - 0.35
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_98] 0 - 0.98
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1673] 0 - 0.61
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1326] 0 - 0.40
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1748] 0 - 0.42
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1921] 0 - 0.70
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_575] 0 - 0.38
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_417] 0 - 0.56
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_764] 0 - 0.27
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1397] 0 - 0.95
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_838] 0 - 4.59
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_945] 0 - 0.51
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_106] 1 True 17.14
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.259s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2332s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2342s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1766] 0 - 0.46
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1631] 1 True 15.39
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.265s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3876s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3885s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1790] 0 - 0.28
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_38] 0 - 0.39
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_876] 0 - 0.49
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1180] 0 - 0.69
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1260] 0 - 0.37
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1982] 1 True 18.67
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8626s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8648s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 355628493 bytes MEM: Free's : 26 free's of 355628493 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_802] 1 True 12.84
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.495s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6662s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6676s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1909] 0 - 19.78
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1058] 1 True 12.93
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.427s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6285s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6302s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18823909 bytes MEM: Free's : 26 free's of 18823909 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1457] 0 - 0.39
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_266] 0 - 0.38
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_2] 0 - 5.02
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1966] 0 - 0.41
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1776] 0 - 0.59
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1679] 1 True 20.29
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.372s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5712s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5735s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 788633021 bytes MEM: Free's : 26 free's of 788633021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_255] 0 - 0.37
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1528] 0 - 0.33
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_400] 0 - 0.36
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1721] 0 - 0.32
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_352] 0 - 0.34
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1517] 0 - 0.35
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1181] 1 True 14.53
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.275s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8627s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8634s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1514] 1 True 14.62
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.163s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2510s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2516s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_308] 0 - 0.55
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1206] 0 - 0.62
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_856] 1 True 13.79
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.233s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2656s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2665s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_820] 1 True 12.22
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with 'align_corners' coordinate_transformation_mode is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.336s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4561s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4569s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_418] 0 - 0.66
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_813] 0 - 2.71
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1732] 0 - 0.44
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_296] 1 True 12.88
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.211s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4295s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4301s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1725] 0 - 0.89
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_858] 0 - 0.41
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1467] 1 True 12.74
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.238s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2967s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2972s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1626] 1 True 12.68
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.245s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5074s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5083s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1722] 0 - 0.59
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_854] 0 - 0.42
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_933] 0 - 0.41
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_258] 0 - 0.38
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_904] 0 - 0.43
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_494] 0 - 0.38
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_331] 1 True 13.68
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.360s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6535s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6549s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1015] 0 - 0.74
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_800] 0 - 0.26
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_696] 0 - 0.48
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1351] 0 - 0.35
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1289] 0 - 0.30
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_390] 0 - 1.09
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1924] 1 True 12.61
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.428s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5954s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5968s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1478] 0 - 0.32
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1525] 0 - 0.40
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_208] 0 - 0.38
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_240] 0 - 2.50
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1353] 0 - 0.78
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1985] 1 True 12.72
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.258s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2644s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2652s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1571] 0 - 0.74
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_20] 0 - 4.43
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_320] 0 - 0.52
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_829] 0 - 0.39
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1731] 0 - 0.45
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1014] 0 - 0.37
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1754] 0 - 0.38
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_737] 0 - 0.41
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1448] 0 - 0.49
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_283] 1 True 15.16
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.295s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3457s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3469s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_406] 0 - 0.34
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1318] 0 - 0.64
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_48] 0 - 0.48
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_261] 1 True 14.08
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.460s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9389s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9417s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_360] 0 - 0.47
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1393] 0 - 0.34
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_269] 0 - 0.27
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1136] 0 - 1.19
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1755] 0 - 0.51
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1628] 0 - 0.36
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_736] 0 - 0.36
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1961] 0 - 0.41
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_136] 1 True 13.58
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.331s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3600s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3613s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 81271645 bytes MEM: Free's : 26 free's of 81271645 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1168] 0 - 0.29
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1743] 0 - 0.35
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_428] 0 - 0.29
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_825] 0 - 0.54
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1656] 0 - 0.26
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1696] 0 - 0.27
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_519] 0 - 0.85
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1160] 0 - 0.40
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1012] 0 - 0.30
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1258] 1 True 11.53
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.456s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7747s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7767s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_660] 1 True 13.07
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.433s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7895s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7911s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19217125 bytes MEM: Free's : 26 free's of 19217125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_700] 0 - 0.29
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_757] 0 - 0.24
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1011] 0 - 0.23
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_496] 0 - 0.23
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1672] 1 True 14.46
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.201s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1911s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1918s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1193] 0 - 0.20
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1073] 0 - 0.22
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1379] 0 - 0.46
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_750] 0 - 0.20
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1143] 0 - 0.35
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1657] 0 - 0.23
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_662] 0 - 0.29
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ---------------------------------------------------------------- | Node | Node Name | Reason | ---------------------------------------------------------------- | Resize | output | Only default antialias = 0 is supported | ---------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_699] 0 - 0.55
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_318] 0 - 0.45
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1894] 0 - 0.59
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_135] 0 - 0.40
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1125] 0 - 0.49
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_922] 0 - 0.53
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_372] 0 - 0.32
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_745] 0 - 0.21
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_968] 0 - 0.30
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_900] 0 - 0.26
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_309] 0 - 0.26
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1147] 1 True 12.72
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.342s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5468s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5480s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1013] 0 - 0.28
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_597] 0 - 0.23
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_973] 0 - 0.21
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_626] 0 - 0.18
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_51] 0 - 0.30
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1809] 0 - 0.37
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1723] 1 True 11.73
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.383s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5790s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5802s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1841] 0 - 0.34
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1237] 0 - 0.26
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1387] 0 - 0.43
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_695] 1 True 13.20
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.360s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5405s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5416s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 531413365 bytes MEM: Free's : 26 free's of 531413365 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_767] 0 - 1.75
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_204] 1 True 10.21
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.258s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1990s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1999s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 81271645 bytes MEM: Free's : 26 free's of 81271645 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1807] 0 - 1.08
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1158] 0 - 0.40
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1665] 0 - 0.39
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_99] 1 True 12.47
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.205s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3482s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3486s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1964] 0 - 0.73
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_667] 1 True 10.95
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.342s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5302s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5309s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 99901277 bytes MEM: Free's : 26 free's of 99901277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_609] 1 True 12.06
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.248s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3623s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3630s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_650] 0 - 0.31
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1446] 0 - 0.34
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1283] 1 True 13.23
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.197s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1724s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1730s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 1096662549 bytes MEM: Free's : 26 free's of 1096662549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_337] 0 - 0.47
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'half_pixel', 'pytorch_half_pixel' and 'asymmetric' coordinate_transformation_mode is supported | ----------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1893] 0 - 0.45
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_275] 0 - 0.33
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------- | Resize | output | Only default keep_aspect_ratio_policy = 'stretch' is supported | --------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_502] 0 - 0.32
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1929] 0 - 0.38
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_523] 0 - 0.24
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1114] 0 - 0.30
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1711] 0 - 0.41
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1802] 0 - 0.35
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1834] 1 True 9.21
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.274s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3036s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3045s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_354] 1 True 11.26
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.146s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1334s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1337s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1633] 1 True 10.78
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.239s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3587s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3593s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1430] 0 - 0.40
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ----------------------------------------------------------------------------- | Node | Node Name | Reason | ----------------------------------------------------------------------------- | Resize | output | Resize is only supported along width and height axis | ----------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_611] 1 True 9.67
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.253s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3713s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3717s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1927] 0 - 0.49
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1554] 0 - 0.46
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1413] 0 - 0.91
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------ | Resize | output | Only 'nearest' and 'linear' resize mode are supported | ------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1242] 0 - 0.36
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1140] 0 - 0.68
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_268] 0 - 0.18
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1692] 0 - 0.34
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_456] 0 - 0.28
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_113] 1 True 4.17
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 0 | --------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1397s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1399s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_925] 0 - 0.27
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1062] 0 - 0.18
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------- | Resize | output | Non-power of 2 scales in layer output is not supported | ------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_362] 0 - 0.31
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1274] 0 - 0.33
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- -------------------------------------------------------------- | Node | Node Name | Reason | -------------------------------------------------------------- | Resize | output | Width and Height scale should be same | -------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_132] 1 True 4.03
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 2 | --------------------------------------------------------------------------- Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1999s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2002s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 788633021 bytes MEM: Free's : 26 free's of 788633021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_610] 0 - 0.07
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------ | Resize | output | 'linear' resize mode is not supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------ ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_227] 0 - 0.11
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'floor' nearest mode is supported when coordinate_transformation_mode is 'asymmetric' | ------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_221] 0 - 0.71
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options [TIDL Import] WARNING: Resize layer - output with scales > 4 is not optimal ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------------------------------------------------------- | Resize | output | Only 'round_prefer_ceil' nearest mode is supported when coordinate_transformation_mode is 'half_pixel' or 'pytorch_half_pixel' | ------------------------------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] =============================
Passed test_tidl_unit.py::test_tidl_unit_operator[Resize_1099] 1 True 2.27
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- --------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | --------------------------------------------------------------------------- | TIDL_ResizeLayer | 1 | 1 | --------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1939s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1942s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= Rerunning network compiler... ========================== [Memory Planning Started] ========================== ------------------------- Network Compiler Traces ------------------------------ Successful Memory Allocation Successful Workload Creation ========================= [Memory Planning Completed] ========================= ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 81271645 bytes MEM: Free's : 26 free's of 81271645 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!